I see that hot reset is something the RC port initiate to have EP reset through link management. ========================================================================== PCIe reset sequences – The PCI Express protocol specifies a hot reset mechanism, where downstream components reset through link notification. Root ports should validate that this mechanism can be applied and the hot reset indication is properly detected by a remote device. Endpoint applications should determine the level of chip reset desired in case of hot reset detection on the link to validate proper functionality. =========================================================================== Does this happen during the enumeration? As this goes in in band, the EP's link should be up. Can someone tell me what are the triggering points for this from RC to EP? Does Linux RC support this? It is supposed to a bit in RC's bridge configuration space that triggers this reset. -- Murali Karicheri Linux Kernel, Keystone -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
