On 03/14/2016 23:42, Bjorn Helgaas wrote:
The nomenclature is confusing, but I think you're reading this backwards. An Upstream Port is on the downstream end of a Link. The "Upstream" definition in the PCIe spec "Terms and Acronyms" section says: The Port on a Switch that is closest topologically to the Root Complex is the Upstream Port. The Port on a component that contains only Endpoint or Bridge Functions is an Upstream Port. I think the spec is saying that PTM must be enabled in a bridge before it is enabled in any device downstream from the bridge.
Thanks for the explanation, looks like back to the drawing board. Do you recommend using pci_walk_bus on all potential PTM masters?
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