Re: [PATCH v2] PCI: tegra: Support per-lane PHYs

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On 02/19/2016 11:01 AM, Thierry Reding wrote:
From: Thierry Reding <treding@xxxxxxxxxx>

The current XUSB pad controller bindings are insufficient to describe
PHY devices attached to USB controllers. New bindings have been created
to overcome these restrictions. As a side-effect each root port now is
assigned a set of PHY devices, one for each lane associated with the
root port. This has the benefit of allowing fine-grained control of the
power management for each lane.

Overall this change looks OK. However, since it encodes aspects of the DT binding (i.e. that the per-port nodes have a phys property in the new scheme), I think it can't be applied until the related DT binding change is accepted.

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c

@@ -883,14 +904,24 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)

+	if (of_get_property(pcie->dev->of_node, "phys", NULL) == NULL) {

Rather than re-parsing DT to determine this, thus duplicating the logic, can't the code store some flag in tegra_pcie_phys_get() indicating which path was taken, and that flag used here? Perhaps that flag could be based on whether pcie->phy is set, although the else block here implies that particular solution won't work.
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