Hi Marc,
On 11/25/2015 5:52 PM, Ray Jui wrote:
Hi Marc,
[...]
+ /* reserve memory for MSI posted writes */
+ msi->msi_cpu = dma_alloc_coherent(pcie->dev,
+ msi->nr_msi_region * MSI_MEM_REGION_SIZE,
+ &msi->msi_dma, GFP_KERNEL);
Same here. Also, what is the exact purpose of that memory? You have a
coherent mapping with the CPU, but you never read from it. So what's
the point?
Yeah I guess I can change this back to kmalloc since coherent memory is
a scarce resource, and the CPU does not need to access the memory, so
there's no cache issue.
I know I have not answered the first part of your question. Let me do
some experiments first and I'll get back to you on that, :)
I did some experiment with the msi_dma here. It looks like it can be any
address as long as it's 4K aligned (i.e., can be from the device address
range instead of the RAM address range). The MSI message data actually
goes to the memory allocated for the event queue (makes sense...), and
never made it to the MSI page memory allocated here. Our arch doc is
just confusing....:(
I saw your comment on the other email thread with Xilinx MSI. I'll set
the address to the base address of the iProc PCIe controller (which is
always 4K aligned).
[...]
Thanks,
M.
Thanks, Marc!
Ray
Thanks again!
Ray
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