On Wed, 25 Nov 2015 05:40:49 +0000 Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx> wrote: > > On Thu, 19 Nov 2015 11:05:23 +0530 > > Bharat Kumar Gogada <bharat.kumar.gogada@xxxxxxxxxx> wrote: > > > > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > > > Signed-off-by: Bharat Kumar Gogada <bharatku@xxxxxxxxxx> > > > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xxxxxxxxxx> > > > Acked-by: Rob Herring <robh@xxxxxxxxxx> > > > --- > > > + > > > +#define MSI_ADDRESS 0xDEED0000 > > > > How did you pick this value? What if it intersect with some actual RAM? > > What if a device actually does DMA to that location? > > > > Wouldn't it make sense to actually pick a real *device* address (hint: > > your MSI controller itself) for this purpose, as the device will never DMA > > there? > > > > > We have already mentioned in previous patch discussion, we don't have > any device address on our SOC for MSI, that's the reason we are > allocating a page for MSI in RAM. Since our memory write is consumed > by bridge and doesn't write to memory, you suggested to use some > random address, so using some random address. This is becoming painful. - "write is consumed by bridge and doesn't write to memory": So why are you using something that has a chance of actually being memory??? Are you in the business of corrupting unsuspecting data? - "we don't have any device address on our SOC for MSI": You have plenty, and that's the whole of your device space. *All of it*. So just take the base address of your PCIe controller, and be done with it. Or your UART. Anything that cannot be DMA'ed to from a PCIe device, and that is downstream of your PCIe bridge. M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
