Am Freitag, den 06.11.2015, 11:59 -0800 schrieb Tim Harvey: > On Fri, Nov 6, 2015 at 1:36 AM, Lucas Stach <l.stach@xxxxxxxxxxxxxx> wrote: > > Am Donnerstag, den 05.11.2015, 06:58 -0800 schrieb Tim Harvey: > >> Freescale has stated [1] that the LVDS clock source of the IMX6 does not pass > >> the PCI Gen2 clock jitter test, therefore unless an external Gen2 compliant > >> external clock source is present and supplied back to the IMX6 PCIe core > >> via LVDS CLK1/CLK2 you can not claim Gen2 compliance. > >> > >> Add a dt property to specify gen1 vs gen2 and check this before allowing > >> a Gen2 link. > >> > > I think I already said this in the last round: there is nothing vendor > > specific in a max-link-speed property. I would really like to have this > > as a common DW PCIe property right from the beginning, so that we don't > > burden us with keeping backward compatibility with vendor specific > > properties when this moves to common code eventually. > > Hi Lucas, > > I did discuss this patch with you off-list but I think I misunderstood > your meaning then. > > So you are asking me to simply rename the properly > 'fsl,max-link-speed' to 'max-link-speed' and the rest of the patch is > good with you? > Yes, rename to max-link-speed. Move parsing of the property to dw_pcie_host_init() (it is a common property, so must be in common code) before the call to ops->host_init and store value into the pcie_port structure with -1 meaning property in DT is missing. imx6_pcie_establish_link can the treat values of -1 and 1 the same, only allowing Gen2 if the value is 2. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
