[Adding Richard Zhu] On Thu, Nov 5, 2015 at 12:58 PM, Tim Harvey <tharvey@xxxxxxxxxxxxx> wrote: > Freescale has stated [1] that the LVDS clock source of the IMX6 does not pass > the PCI Gen2 clock jitter test, therefore unless an external Gen2 compliant > external clock source is present and supplied back to the IMX6 PCIe core > via LVDS CLK1/CLK2 you can not claim Gen2 compliance. > > Add a dt property to specify gen1 vs gen2 and check this before allowing > a Gen2 link. > > We default to Gen1 if the property is not present because at this time there > are no IMX6 boards in mainline that 'input' a clock on LVDS CLK1/CLK2. > > In order to be Gen2 compliant on IMX6 you need to: > - have a Gen2 compliant external clock generator and route that clock back > to either LVDS CLK1 or LVDS CLK2 as an input. > (see IMX6SX-SabreSD reference design) > - specify this clock in the pcie node in the dt > (ie IMX6QDL_CLK_LVDS1_IN or IMX6QDL_CLK_LVDS2_IN instead of > IMX6QDL_CLK_LVDS1_GATE which configures it as a CLK output) > > [1] https://community.freescale.com/message/453209 > > Signed-off-by: Tim Harvey <tharvey@xxxxxxxxxxxxx> > > This is an RFC because I'm assuming the decision to default to Gen1 link only > is going to ruffle some feathers. My understanding is that if you do not > use an external Gen2 compliant clockgen for peripepherals 'and' the IMX6 core > you should not claim Gen2 compliance. This was not obvious on original IMX6 > reference designs and I believe the jitter issue was discovered by Freescale > later and future reference designs were modified to state you need an ext > clockgen for Gen2 compliance. Looks good to me: Reviewed-by: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
