I'm seeing two problems with the current PCI framework when it comes to
end-to-end CRC (ECRC) and Max Read Request Size.
The problem with ECRC is that it blindly enables ECRC generation on
devices without checking if it is supported by the entire bus with
ECRC=on option.
ECRC check can be enabled on all devices but ECRC generation on the root
complex and switches needs to be set only if all devices support ECRC
checking.
I'm thinking of making changes in this area to cover this gap with
ECRC=safe option.
The other problem I'm seeing is about the maximum read request size. If
I choose the PCI bus performance mode, maximum read request size is
being limited to the maximum payload size.
I'd like to add a new mode where I can have bigger read request size
than the maximum payload size.
Opinions?
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
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