Am Montag, den 12.10.2015, 09:31 -0300 schrieb Fabio Estevam: > On Mon, Oct 12, 2015 at 7:28 AM, Lucas Stach <l.stach@xxxxxxxxxxxxxx> wrote: > > > Actually the TRM states that i.MX6 is using the same narrower mask of > > 0x1f for the LTSSM state, so another reason to just use that. > > The manual I have seems to tell a different value :-) > > Please check: http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf > > "48.12.11 > Debug Register 0 (PCIE_PL_DEBUG0)" > > says "[5:0]: xmlh_ltssm_state LTSSM current state. See source for encodings" > Urgh. Seems we got confused by all the different defines. In fact [5:0] is 0x1f, so i.MX6 uses the same mask as Keystone, yet the common and shared header now states a mask of 0x3f with Keystone being the exception. That doesn't reflect reality which isn't nice IMHO. I think it would be better to just use 0x1f as the LTSSM mask in the shared header and use this for all drivers until a need arises for using the extra bit on SPEAR. Regards, Lucas -- Pengutronix e.K. | Lucas Stach | Industrial Linux Solutions | http://www.pengutronix.de/ | -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
