This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts use PCIe IP core from Synopsys, So this driver is based on designware PCIe driver. Hip05 is an ARMv8 architecture SoC. It should be able to use ARM64 PCIe API in designware PCIe driver. So this patch also adds ARM64 support for designware pcie. This patchset is based on v4.3-rc1. Change from v8: - Rebase on v4.3-rc1. - Add Tested-by from Gabriel and Minghuan. - Remove ITS domain parsing in msi_host_init in pcie-hisi.c, no need this as PCI core does related job. Add ITS base address parsing in msi_host_init. - Change vmid/asid table configuration, previous configuration was wrong. - Add wr_own_conf callback in pcie-hisi.c. - Use subsys_initcall to init hisi PCIe. Change from v7: - Remove pp->root_bus_nr = 0 in dra7xx, exynos, imx6, keystone, layerscape, spear13xx. Pass pp->busn->start to pci_create_root_bus as root bus number. - Remove bus-range parsing in pcie-hisi.c. Change from v6: - Add Pratyush's Acked-by for 1/6 and 2/6. - Add James' Tested-by for 3/6. Change from v5: - Merge 1/6 in this series, discussion about this can be found in [1] Change from v4: - Change the author of 1/5 to Gabriele. - Modify problems in 3/5 pointed by Bjorn. - Modify spelling problems in 4/5. Change from v3: - Change 1/5 to what Gabriele suggested. - Use win->__res.start to get *_mod_base in 2/5, this fix a bug in v3 series. Change from v2: - Move struct pci_dev *dev and struct pci_sys_data *sys in pcibios_align_resource in 1/5. - Add Gabriele's codes in 2/5 which delete unnecessary information parse and use of_pci_get_host_bridge_resources for both ARM32 and ARM64. - Add maintainer patch 5/5. Change from RFC v1: - Add 1/4 patch by Arnd which removes align_resource callback in ARM pcibios_align_resource. - Change head file in pcie-designware from asm/hardirq.h to linux/hardirq.h. - Set pp->root_bus_nr = 0 in dra7xx, exynos, imx6, keystone, layerscape, spear13xx. - Remove unnecessary parentheses of some macros in pcie-hisi. - Use macro to replace some magic values. - Merge two loops together and add some comments about it in context_config function in pcie-hisi. - Modify some value of items in pcie node example in binding document. Change from RFC: - delete dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci, merge related operations into dw_pcie_host_init. Link of v8: - http://www.spinics.net/lists/linux-pci/msg44192.html Link of v7: - http://www.spinics.net/lists/devicetree/msg90690.html Link of v6: - http://www.spinics.net/lists/linux-pci/msg43669.html Link of v5: - http://www.spinics.net/lists/devicetree/msg87959.html Link of v4: - http://www.spinics.net/lists/arm-kernel/msg433050.html Link of v3: - http://www.spinics.net/lists/linux-pci/msg42539.html Link of v2: - http://www.spinics.net/lists/linux-pci/msg41844.html Link of RFC v1: - http://www.spinics.net/lists/linux-pci/msg41305.html Link of RFC: - http://www.spinics.net/lists/linux-pci/msg40434.html [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/359741.html Zhou Wang (4): PCI: designware: Add ARM64 support PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Documentation: DT: Add HiSilicon PCIe host binding MAINTAINERS: Add pcie-hisi maintainer gabriele paoloni (2): PCI: designware: move calculation of bus addresses to DRA7xx ARM/PCI: remove align_resource in pci_sys_data .../devicetree/bindings/pci/hisilicon-pcie.txt | 46 +++ MAINTAINERS | 7 + arch/arm/include/asm/mach/pci.h | 6 - arch/arm/kernel/bios32.c | 12 +- drivers/pci/host/Kconfig | 8 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pci-dra7xx.c | 13 + drivers/pci/host/pci-keystone-dw.c | 2 +- drivers/pci/host/pcie-designware.c | 245 +++++----------- drivers/pci/host/pcie-designware.h | 14 +- drivers/pci/host/pcie-hisi.c | 310 +++++++++++++++++++++ 11 files changed, 476 insertions(+), 188 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt create mode 100644 drivers/pci/host/pcie-hisi.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
