On 2015. 8. 25., at PM 7:35, Zhou Wang <wangzhou1@xxxxxxxxxxxxx> wrote: > > The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. Here change > this mask to proper value. > > In fact, for DesignWare PCIe IP version 4.4, it only uses bit8~12 to indicate > number of lanes. Original mask will bring a mistake. NAK The definitions of bits of registers should be defined based on hardware manual such as datasheet, databook. According to the databook, the bits [16:8] are defined for NUM_OF_LANES. In the future, if 16 lanes or 32 lanes is supported and 12th bit or 13th bit is used, what will you do? Then, in the version 4.4 IP, the bits[16:13] are used for other usage? Best regards, Jingoo Han > Signed-off-by: Zhou Wang <wangzhou1@xxxxxxxxxxxxx> > --- > drivers/pci/host/pcie-designware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index 69486be..eb549b9 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c > @@ -35,7 +35,7 @@ > > #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C > #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) > -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8) > +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) > #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) > #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) > #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) > -- > 1.9.1 > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
