On Intel Edison we have an interesting implementation of x86 platform without legacy PIC and with specific PCI. There are devices which are not using interrupt line 0, but have it assigned in the PCI configuration. By default first come gets it, though the first eMMC host controller is the actual user for IRQ0. So, this series provides a quirk (patch 1) to resolve the issue, a small fix of error code (patch 2), and a sparse warning fix (patch 3). Changelog v3: - address Thomas' comments - massage changelog (what Thomas proposed) Changelog v2: - rearrange patches 1 and 2 to provide fix first with Fixes: tag - append patch 3 - rebase on top of recent linux-next Andy Shevchenko (3): x86/pci/intel_mid_pci: work around for IRQ0 assignment x86/pci/intel_mid_pci: propagate actual return code x86/pci/intel_mid_pci: fix a sparse warning arch/x86/pci/intel_mid_pci.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) -- 2.4.6 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
