On 07/16/2015 10:09 AM, Marc Zyngier wrote:
On 16/07/15 17:50, David Daney wrote:
[...]
Patch 5 has established that you're using "virtual wire" SPIs, so we need to work on exposing that with the normal kernel abstraction, and not by messing with the internals of the GIC.Agreed. The MSI system has pci_enable_msix()/pci_disable_msix(). I would propose something like: struct gic_spi_entry { int spi /* SPI number */ int irq; /* kernel irq number mapped to the spi*/ u32 msg; /* message to be written */ u64 assert_addr; u64 deassert_addr; }; /* Fill in the SPI processing information */ int gic_map_spi(int spi, struct gic_spi_entry *data);Neither. The way to do it is to make this a *separate* IRQ domain stacked onto the SPI domain. No funky hook on the side. If it doesn't go through the normal kernel API, it doesn't reach the GIC.
Yes, the irqdomain does handle mapping SPI -> irq, and the message can be derived from the SPI. However, the irqdomain infrastructure cannot supply values for either assert_addr or deassert_addr.
Those are needed in order to use SPI. How would you suggest that they be obtained?
David Daney
M.
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