On Intel Edison we have an interesting implementation of x86 platform without legacy PIC and with specific PCI. There are devices which are not using interrupt by some reasons, but have them as IRQ0 in the PCI configuration. Suprisingly the first eMMC host controller is the actual user for IRQ0. Since we have serial driver implemented that enumerates unused serial IP (one of four) which has IRQ0 assigned we, in case it gets it first by pci_enable_device(), lost a possibility to probe eMMC. So, this series provides a quirk (patch 1), small fix of error code (patch 2), and sparse warning fix (patch 3). Changelog v2: - rearrange patches 1 and 2 to provide fix first with Fixes: tag - append patch 3 - rebase on top of recent linux-next Andy Shevchenko (3): x86/pci/intel_mid_pci: work around for IRQ0 assignment x86/pci/intel_mid_pci: propagate actual return code x86/pci/intel_mid_pci: fix a sparse warning arch/x86/pci/intel_mid_pci.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
