Rajat Jain <rajatjain <at> juniper.net> writes:
>
> > >
> > > cpld = (u8 *)sam->membase;
> > > for (i = 0; i < 0x40; i++) {
> > > pr_emerg(" %02X", cpld[i]);
> > > }
> > >
> > >
> > > My questions:
> >
> > Maybe a silly question, but does the device support byte-width
access to this
> > space? Thanks,
> >
>
> Voila!!!!! That was the issue - the device only supports 4byte
accesses.
>
> Thanks a lot Alex!
>
> I feel so stupid. Sometimes the most silly items get overlooked.
>
> Thanks again,
>
> Rajat
>
Hi every one
I have completion time out issue with a different topology.
my topology is as below
CPU is x86-64bit
cpu === pcie switch === pcie end devices
completion time out is reported (rarely) on cpu root port connected to
pcie switch.
Since there are multiple devices (accessed by multiple drivers) under
the pcie switch and the issue is rarely seen,I am not able to figure out
which device is causing the issue.
could some one please throw some light on what other factors cause
completion time out other than access width ?
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