address cell and size cells parameter in PCIE

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



HI I have a confusion regarding address cell and size cell values for pci
node in device tree. Is it compulsary that address cell value is 3 and size
cell value is 2 for PCIE.
On what basis the values of address cell and size cell should be assigned.



--
To unsubscribe from this list: send the line "unsubscribe linux-pci" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html




[Index of Archives]     [DMA Engine]     [Linux Coverity]     [Linux USB]     [Video for Linux]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [Greybus]

  Powered by Linux