On Thu, Nov 20, 2014 at 07:51:40AM +1100, Benjamin Herrenschmidt wrote: >On Wed, 2014-11-19 at 10:23 -0700, Bjorn Helgaas wrote: >> >> Yes, I've read that many times. What's missing is the connection between a >> PE and the things in the PCI specs (buses, devices, functions, MMIO address >> space, DMA, MSI, etc.) Presumably the PE structure imposes constraints on >> how the core uses the standard PCI elements, but we don't really have a >> clear description of those constraints yet. > >Right, a "PE" is a HW concept in fact in our bridges, that essentially is >a shared isolation state between DMA, MMIO, MSIs, PCIe error messages,... >for a given "domain" or set of PCI functions. > >The techniques of how the HW resources are mapped to PE and associated >constraints are slightly different from one generation of our chips to >the next. In general, P7 follows an architecture known as "IODA" and P8 >"IODA2". I'm trying to get that spec made available via OpenPower but >that hasn't happened yet. > >In this case we mostly care about IODA2 (P8), so I'll give a quick >description here. Wei, feel free to copy/paste that into a bit of doco >to throw into Documentation/powerpc/ along with your next spin of the patch. > Got it. I will add more description in powerpc directory. -- Richard Yang Help you, Help me -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
