On Mon, Oct 27, 2014 at 01:17:32PM +0800, Richard Zhu wrote:
> From: Richard Zhu <r65037@xxxxxxxxxxxxx>
>
> For boards without a reset GPIO we skip the delay between enabling the
> pcie_ref_clk and touching the RC registers for configuration.
> This hangs the system if there isn't a proper delay to ensure the clocks
> are settled in the DW PCIe core.
>
> Also iMX6Q always needs an additional 10us delay to make sure the reset
> is propagated through the core, as we don't have an explicitly
> controlled reset input on this SoC.
>
> Signed-off-by: Richard Zhu <richard.zhu@xxxxxxxxxxxxx>
> Tested-by: Fabio Estevam <fabio.estevam@xxxxxxxxxxxxx>
> Acked-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx>
I added the regression info to the changelog and applied this to for-linus
for v3.18, thanks!
> ---
> drivers/pci/host/pci-imx6.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
> index 233fe8a..eac96fb 100644
> --- a/drivers/pci/host/pci-imx6.c
> +++ b/drivers/pci/host/pci-imx6.c
> @@ -275,15 +275,22 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
> goto err_pcie;
> }
>
> - /* allow the clocks to stabilize */
> - usleep_range(200, 500);
> -
> /* power up core phy and enable ref clock */
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
> + /*
> + * the async reset input need ref clock to sync internally,
> + * when the ref clock comes after reset, internal synced
> + * reset time is too short , cannot meet the requirement.
> + * add one ~10us delay here.
> + */
> + udelay(10);
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
>
> + /* allow the clocks to stabilize */
> + usleep_range(200, 500);
> +
> /* Some boards don't have PCIe reset GPIO. */
> if (gpio_is_valid(imx6_pcie->reset_gpio)) {
> gpio_set_value(imx6_pcie->reset_gpio, 0);
> --
> 1.9.1
>
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