> From: Felipe Balbi [mailto:balbi@xxxxxx] > Sent: Friday, October 17, 2014 8:00 AM > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote: > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation > > board. > > > > Signed-off-by: Huang Rui <ray.huang@xxxxxxx> > > --- > > drivers/usb/dwc3/core.c | 7 ++++++- > > drivers/usb/dwc3/dwc3-pci.c | 3 ++- > > drivers/usb/dwc3/platform_data.h | 1 + > > 3 files changed, 9 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > > index 3ccfe41..4a98696 100644 > > --- a/drivers/usb/dwc3/core.c > > +++ b/drivers/usb/dwc3/core.c > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc) > > if (dwc->quirks & DWC3_QUIRK_TX_DEEPH) > > reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1); > > > > + if (dwc->quirks & DWC3_QUIRK_SUSPHY) > > should be: > > if (!dwc->suspend_usb3_phy_quirk) > > > + reg |= DWC3_GUSB3PIPECTL_SUSPHY; > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling > that bit. Am I missing something ? Paul ? It looks to me that Huang's patch is enabling that bit, not disabling it. Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch series you just posted). According to the databook, both of those bits should be set to 1 after the core initialization has completed. So I think the driver should be changed to enable both of those by default, and then maybe you want quirks to disable them if there is some platform out there which needs that. -- Paul -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
