At Wed, 01 Oct 2014 10:09:28 +0200,
Takashi Iwai wrote:
>
> At Wed, 01 Oct 2014 17:41:29 +1000,
> Benjamin Herrenschmidt wrote:
> >
> > On Wed, 2014-10-01 at 09:38 +0200, Takashi Iwai wrote:
> >
> > > > diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
> > > > index 3e6d22d..2b679d5 100644
> > > > --- a/sound/pci/hda/hda_intel.c
> > > > +++ b/sound/pci/hda/hda_intel.c
> > > > @@ -297,7 +297,7 @@ enum {
> > > > /* quirks for ATI/AMD HDMI */
> > > > #define AZX_DCAPS_PRESET_ATI_HDMI \
> > > > (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
> > > > - AZX_DCAPS_NO_MSI64)
> > > > + AZX_DCAPS_NO_MSI64 | AZX_DCAPS_NO_64BIT)
> > >
> > > The only concern is that this will disable 64bit DMA also on x86 where
> > > it has been working fine. Can we add an ifdef CONFIG_PPC for this?
> >
> > I don't like that approach because technically the chip doesn't do
> > 64-bit DMA ... it does something like 40 or 48 (might actually depend on
> > the chip version) and for all I know it will break on future x86 with
> > more memory or other platforms with similar address encodings as
> > powerpc...
> >
> > The right thing might be to get the exact number of bits and do the
> > appropriate dma_set_mask() like the graphics driver does, but that's a
> > bit tricky unless we add a DMA mask field in that big array of chips in
> > there...
>
> I think setting the dma mask explicitly would be a better approach
> although it results in a bit bigger change. At least, it would impact
> less than forcing 32bit DMA, as most desktop machines have less than
> 40bit address. How about a patch like below?
Oops, it obviously doesn't work with AMD ID... Fixed in below.
Takashi
-- 8< --
From: Takashi Iwai <tiwai@xxxxxxx>
Subject: [PATCH v2] ALSA: hda - Limit 40bit DMA for AMD HDMI controllers
AMD/ATI HDMI controller chip models, we already have a filter to lower
to 32bit DMA, but the rest are supposed to be working with 64bit
although the hardware doesn't really work with 63bit but only with 40
or 48bit DMA. In this patch, we take 40bit DMA for safety for the
AMD/ATI controllers as the graphics drivers does.
Signed-off-by: Takashi Iwai <tiwai@xxxxxxx>
---
sound/pci/hda/hda_intel.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index aa302fb03fc5..99b367bd9b1b 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1482,6 +1482,7 @@ static int azx_first_init(struct azx *chip)
struct snd_card *card = chip->card;
int err;
unsigned short gcap;
+ unsigned int dma_bits = 64;
#if BITS_PER_LONG != 64
/* Fix up base address on ULI M5461 */
@@ -1518,9 +1519,14 @@ static int azx_first_init(struct azx *chip)
gcap = azx_readw(chip, GCAP);
dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
+ /* AMD devices support 40 or 48bit DMA, take the safe one */
+ if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
+ dma_bits = 40;
+
/* disable SB600 64bit support for safety */
if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
struct pci_dev *p_smbus;
+ dma_bits = 40;
p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
PCI_DEVICE_ID_ATI_SBX00_SMBUS,
NULL);
@@ -1550,9 +1556,11 @@ static int azx_first_init(struct azx *chip)
}
/* allow 64bit DMA address if supported by H/W */
- if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
- pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
- else {
+ if (!(gcap & AZX_GCAP_64OK))
+ dma_bits = 32;
+ if (!pci_set_dma_mask(pci, DMA_BIT_MASK(dma_bits))) {
+ pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(dma_bits));
+ } else {
pci_set_dma_mask(pci, DMA_BIT_MASK(32));
pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
}
--
2.1.0
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