On Tuesday 16 September 2014, Lian Minghuan-B31939 wrote: > >>>> + ranges = <0x81000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00010000 /* downstream I/O */ > >>>> + 0x82000000 0x0 0x00000000 0x41 0x00000000 0x1 0x00000000>; /* non-prefetchable memory */ > >>> Are these ranges hardcoded in the SoC, or are they the result of iATU > >>> settings? If the latter, who configures it and why no prefetchable > >>> region? > >> [Minghuan] 400000_0000 - 480000_0000 is hardcode assigned to PEX1. > >> I separates from this 32 region 1M for IO, 4G for non-prefetchable memory. > >> 4G is the max size iATU supported. > >> IO and memory region will be set to iATU by pci-designware.c > >> Because both powerpc and imx do not set prefechable memory, > >> so I do not assign prefetchable memory either. > > If there's spare room in the addres space for a prefetchable region, why > > not make one, regardless of what PPC and IMX do? > > > > FWIW, I believe that ARMv8 can make better use of a prefetchable region > > due to the "gathering" storage attribute, so even if you don't use one > > on LS1021A consider using one on ARMv8-based LS chips. > [Minghuan] Ok, I will add 4G prefetchable memory region. I guess that means you still can't support devices that require 64-bit BARs, right? 4GB may be too small for some devices. Do I read this right that you could have multiple adjacent 4GB areas but are limited on registers to set up these areas? Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
