Hello All,
I am having trouble understanding what memory ranges go through the PCIe
root bridge on a Haswell CPU (what I have in my system) and similarly on
other modern CPUs. From what I can gather from sources online (including
many datasheets) is that the PCIE root complex contains a PCI host bridge,
which produces 1 PCI root bridge (ACPI\PNP0A08). This root bridge then
forwards certain memory ranges onto the PCI/PCIe bus.
First of all if I take something like PAM registers, when something is
written to this address the PAM register forwards it to DMI (if set to do so
E.G. 0xD0000), so this transaction never goes through the PCI root bridge?
What's confusing is if I look at the DSDT ACPI table and look at the
ACPI\PNP0A08 device, it says that the PAM registers ranges go through it. I
guess this is just for an OS purpose as it doesn’t need to know what exact
ranges go through the root bridge? I'm not entirely sure on that and if
anyone could clarify it would be appreciated.
As well as the PAM register ranges for the root bridge it also has the PCIe
device memory range, which in my case is 0xC0000000 – 0xFEAFFFFF, now does
that mean that anything above that range isn't going through the PCI root
bridge, or is it just like that so an OS doesn't try map a device in that
region. If I look at the Haswell datasheet it has small regions in that area
between things like APIC and BIOS that reach the DMI.
It seems as if the PCI root bridge is using some sort of subtractive
decoding that picks up whatever isn't sent to DRAM etc. and to make it easy
for an OS the BIOS gives it a block of address space.
Finally, I was on a forum related to external GPUs, and some Windows users
didn’t have enough space to map the device below 4GB. To resolve this they
manually edited the DSDT table and added another entry above the 4GB
barrier, now Windows mapped the GPU in the 64bit space. Now I presume
changing the entry in the DSDT table didn't make any difference to how the
hardware was set up, it just told the OS that the root bridge will in fact
pick up this address range and therefore it knew it could map it there.
So am I write in thinking the ranges in the ACPI table are for the OSs
purpose, and don't actually have to accurately represent what the hardware
does.
..and does anyone know what ranges do actually go through a single PCIe root
bridge on a modern system?
If anyone could help it would be greatly appreciated :)
Kind Regards,
Robert
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