Hi Thomas, This piece of code is inherited from current IOAPIC driver and I think it's a workaround for some weird platforms. For normal platforms with both 8259A and IOAPIC controllers, legacy ISA IRQs should be connected to both 8259A and IOAPIC pins (ignore timer and cascade IRQs for simplicity). According to comments in current kernel, there are some platforms on which: 1) some ISA IRQs are only connected to 8259A controllers. 2) the corresponding IOAPIC pins are connected to some non-ISA IRQs. For such platforms, IRQ0-15 are used for ISA IRQs and another 16 IRQs just above gsi_top are reserved for IOAPIC pins 0-15 which are connected to non-ISA IRQs. I have no real experience with such a platform, but just guessing possible cases according to kernel comments and "Multiple Processor Specification". Please look at these two pictures for quick reference. http://www.manualslib.com/manual/77733/Intel-Multiprocessor.html?page=31#manual http://www.manualslib.com/manual/77733/Intel-Multiprocessor.html?page=63#manual Thanks! Gerry On 2014/6/10 7:22, Thomas Gleixner wrote: > On Mon, 9 Jun 2014, Jiang Liu wrote: >> unsigned int arch_dynirq_lower_bound(unsigned int from) >> { >> - return from < nr_irqs_gsi ? nr_irqs_gsi : from; >> + unsigned int min = gsi_top + NR_IRQS_LEGACY; > > Why is this gsi_top + NR_IRQ_LEGACY? The legacy interrupts are part of > the gsi space, aren't they? > > Thanks, > > tglx > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
