Refine SFI to use common irqdomain map interface to program IOAPIC pins,
so we can unify the callsite to progam IOAPIC pins.
Signed-off-by: Jiang Liu <jiang.liu@xxxxxxxxxxxxxxx>
---
arch/x86/pci/intel_mid_pci.c | 17 +++++++----------
arch/x86/platform/intel-mid/sfi.c | 18 +++++++++---------
arch/x86/platform/sfi/sfi.c | 4 +++-
3 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 84b9d672843d..f6f3de857baa 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -208,23 +208,20 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
static int intel_mid_pci_irq_enable(struct pci_dev *dev)
{
- u8 pin;
- struct io_apic_irq_attr irq_attr;
-
- pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+ int ioapic, polarity;
/*
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device.
*/
- irq_attr.ioapic = mp_find_ioapic(dev->irq);
- irq_attr.ioapic_pin = dev->irq;
- irq_attr.trigger = 1; /* level */
+ ioapic = mp_find_ioapic(dev->irq);
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
- irq_attr.polarity = 0; /* active high */
+ polarity = 0; /* active high */
else
- irq_attr.polarity = 1; /* active low */
- io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
+ polarity = 1; /* active low */
+ if (mp_set_pin_attr(ioapic, dev->irq, 1, polarity, dev_to_node(dev)))
+ return -EBUSY;
+ mp_map_gsi_to_irq(dev->irq, 1);
return 0;
}
diff --git a/arch/x86/platform/intel-mid/sfi.c b/arch/x86/platform/intel-mid/sfi.c
index 994c40bd7cb7..3fe5c23ba1c5 100644
--- a/arch/x86/platform/intel-mid/sfi.c
+++ b/arch/x86/platform/intel-mid/sfi.c
@@ -434,6 +434,7 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
struct devs_id *dev = NULL;
int num, i;
int ioapic;
+ int polarity;
struct io_apic_irq_attr irq_attr;
sb = (struct sfi_table_simple *)table;
@@ -450,30 +451,29 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
*/
ioapic = mp_find_ioapic(irq);
if (ioapic >= 0) {
- irq_attr.ioapic = ioapic;
- irq_attr.ioapic_pin = irq;
- irq_attr.trigger = 1;
if (intel_mid_identify_cpu() ==
INTEL_MID_CPU_CHIP_TANGIER) {
if (!strncmp(pentry->name,
"r69001-ts-i2c", 13))
/* active low */
- irq_attr.polarity = 1;
+ polarity = 1;
else if (!strncmp(pentry->name,
"synaptics_3202", 14))
/* active low */
- irq_attr.polarity = 1;
+ polarity = 1;
else if (irq == 41)
/* fast_int_1 */
- irq_attr.polarity = 1;
+ polarity = 1;
else
/* active high */
- irq_attr.polarity = 0;
+ polarity = 0;
} else {
/* PNW and CLV go with active low */
- irq_attr.polarity = 1;
+ polarity = 1;
}
- io_apic_set_pci_routing(NULL, irq, &irq_attr);
+ if (mp_set_pin_attr(ioapic, irq, 1, polarity, NUMA_NO_NODE))
+ return -EBUSY;
+ mp_map_gsi_to_irq(dev->irq, 1);
}
} else {
irq = 0; /* No irq */
diff --git a/arch/x86/platform/sfi/sfi.c b/arch/x86/platform/sfi/sfi.c
index 2c3522dfa05d..91e5046efae9 100644
--- a/arch/x86/platform/sfi/sfi.c
+++ b/arch/x86/platform/sfi/sfi.c
@@ -71,7 +71,9 @@ static int __init sfi_parse_cpus(struct sfi_table_header *table)
#endif /* CONFIG_X86_LOCAL_APIC */
#ifdef CONFIG_X86_IO_APIC
-static struct irq_domain_ops sfi_ioapic_irqdomain_ops;
+static struct irq_domain_ops sfi_ioapic_irqdomain_ops = {
+ .map = mp_irqdomain_map,
+};
static struct irq_domain *sfi_ioapic_create_irqdomain(int ioapic, void *arg)
{
--
1.7.10.4
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