On Wednesday, May 14, 2014 1:14 AM, Phil Edworthy wrote:
>
> Hi,
>
> I am currently writing another driver that uses the Synopsys Designware
> PCIe host controller driver.
>
> In general, it all looks good thanks to all involved in this driver.
> One area that I am having a little problem with is the interrupts.
> According to the documentation I have, the module has separate
> interrupts for INTA, INTB, INTC, INTD, MSI, AER, bandwidth management,
> PME (and possibly a couple of others as well).
>
> However, so far it looks like the upstream implementations just use
> a single interrupt for the module, is that correct? I notice that some
> DT bindings include other interrupts that are not part of the Designware
> PCIe controller, but that's not what I'm talking about.
(+cc Mohit Kumar, Pratyush Anand, Marek Vasut, Kishon Vijay Abraham I,
Lucas Stach, Tim Harvey, Arnd Bergmann)
PCIe Interrupt mapping is specific for SoC.
In the case of Exynos, there are three interrupts for
Exynos PCIe; INTx, MSI, PHY Link, respectively as below.
./arch/arm/boot/dts/exynos5440.dtsi
interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
<0 20 0>: PCIe RC0 pulse interrupt,
INTA, INTB, INTC and INTD, etc
<0 21 0>: PCIe RC0 level interrupt,
MSI, etc
<0 22 0>: PCIe RC0 special interrupt,
PHY Link related interrupts, etc
So, there are three lines between GIC and PCIe. Also, IRQ mappings
for other SoCs are different.
For example, the IMX6 maps INTA/B/C/D to ARM GIC IRQ 155/154/153/152
respectively.
Then, how many lines are there between GIC and PCIe in your SoC?
How does your SoC map interrupts to GIC?
>
> In existing implementations, does the hardware just OR
> all these interrupts together?
>
Sorry, I cannot understand; other engineers will answer.
Best regards,
Jingoo Han
> Thanks
> Phil
--
To unsubscribe from this list: send the line "unsubscribe linux-pci" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
