Hi Marek: > -----Original Message----- > From: linux-pci-owner@xxxxxxxxxxxxxxx [mailto:linux-pci-owner@xxxxxxxxxxxxxxx] > On Behalf Of Marek Vasut > Sent: Wednesday, April 02, 2014 6:35 PM > To: Kishon Vijay Abraham I > Cc: Mohit KUMAR DCG; Jingoo Han; 'Bjorn Helgaas'; linux-pci@xxxxxxxxxxxxxxx; > Pratyush ANAND; Zhu Richard-R65037 > Subject: Re: [PATCH] PCI: designware: Remove unnecessary RC BAR setting > > On Wednesday, April 02, 2014 at 07:34:15 AM, Kishon Vijay Abraham I wrote: > > On Wednesday 02 April 2014 11:03 AM, Mohit KUMAR DCG wrote: > > > Hello Jingoo, > > > > > >> -----Original Message----- > > >> From: Jingoo Han [mailto:jg1.han@xxxxxxxxxxx] > > >> Sent: Wednesday, April 02, 2014 10:53 AM > > >> To: Mohit KUMAR DCG > > >> Cc: 'Bjorn Helgaas'; linux-pci@xxxxxxxxxxxxxxx; Pratyush ANAND; > > >> 'Marek Vasut'; 'Richard Zhu'; 'Kishon Vijay Abraham I' > > >> Subject: Re: [PATCH] PCI: designware: Remove unnecessary RC BAR > > >> setting > > >> > > >> On Wednesday, April 02, 2014 1:57 PM, Mohit KUMAR DCG wrote: > > >>> On Tuesday, April 01, 2014 4:00 PM, Jingoo Han wrote: > > >>>> According to the spec, the synopsys core does not implement the > > >>>> optional BARs such as BAR0/1. This is based on the assumption > > >>>> that the RC host probably has registers on some other internal > > >>>> bus and has knowledge and setup access to these registers already. > > >>>> So, remove unnecessary RC BAR setting. > > >>> > > >>> - Normally BARs in RC are not used but somehow available in the > > >>> design. One possible BAR use can be if RC has some memory > > >>> connected to > > >> > > >> the BAR that needs to be accessed through link. > > >> > > >>> Otherwise we can ignore BARs setup here. > > >> > > >> Hi Mohit KUMAR DCG, > > >> > > >> Thank you for your feedback. > > >> > > >> I want to know whether or not other SoCs such as ST, Freescale, TI > > >> support BAR0/BAR1. If no SoC supports BAR0/BAR1, the unnecessary RC > > >> BAR setting code should be removed. > > > > > > - We are not currently using RC's BAR0/1 in any application but no > > > such restriction from HW as ST SoCs support BARs in HW design. > > > > Neither do we in DRA7xx. > > I suspect that means we should keep the code to make sure the registers are > configured correctly, no? > > Richard, can you comment on MX6 please ? [Richard] Sorry to reply late. I'm engaged in another stuff in the past days. i.MX6 pcie doesn't use RC's BAR0/1 in applications either. > > Best regards, > Marek Vasut > -- > To unsubscribe from this list: send the line "unsubscribe linux-pci" in the > body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at > http://vger.kernel.org/majordomo-info.html > Best Regards Richard Zhu -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
