Hello, > -----Original Message----- > From: linux-pci-owner@xxxxxxxxxxxxxxx [mailto:linux-pci- > owner@xxxxxxxxxxxxxxx] On Behalf Of Valentin Longchamp > Sent: Wednesday, March 19, 2014 5:47 AM > To: linuxppc-dev@xxxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx > Subject: EDAC PCIe errors when scannning the bus > > Hello, > > We have a board that is based on Freescale's P2041 SoC. The boards has 2 > PCIe buses with this topology: > > PCIe 0 <---> PEX8505 switch <---> 4 network devices PCIE 2 <---> FPGA > > On 3.10.33 + a subset of the Freescale SDK 1.4 patches, both PCIe buses > work well and we are able to use the devices on them. > > For each bus, I however keep getting EDAC PCIe errors at the very first > stage of bus enumeration (please see the attached kernel log, with some > debug output from arch/powerpc/kernel/pci-common.c and > drivers/pci/probe.c) for both buses. > > My current "understanding" of the situation is such: since > PCI_PROBE_NORMAL is used, pcibios_scan_phb() calls pci_scan_child_bus() > that does a pci_scan_slot() on the bus for 32 slots. The first > pci_scan_slot() is successful and it discovers the P2041's PCIe > Controller. All the 31 other pci_scan_slot() calls generate an EDAC PCIe > error, that is triggered by the configuration read transaction to read > an hypothetical vendor ID of a device on the bus. This is relevant with > that is reported by the EDAC error handler (all the 31 are the same): > > > PCIE error(s) detected > > PCIE ERR_DR register: 0x00020000 > > ICCA bit is set: Access to an illegal configuration space from > PEX_CONFIG_ADDR/PEX_CONFIG_DATA was detected. > > > PCIE ERR_CAP_STAT register: 0x80000001 > > To is set: Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA. > > > PCIE ERR_CAP_R0 register: 0x00000800 > > FMT: 0b00, TYPE: 0b00100 (Config read I guess) > > > PCIE ERR_CAP_R1 register: 0x00000000 > > PCIE ERR_CAP_R2 register: 0x00000000 > > PCIE ERR_CAP_R3 register: 0x00000000 > > Afterwards, pci_scan_child_bus() calls pcibios_fixup_bus (that maybe > helps ?). > From here, since the P2041's PCIe Controller is a bridge, > pci_scan_bridge is called for this bus and all the devices are detected > without having any configuration transaction causing EDAC errors. > > Has someone already observed such a behavior ? Why do these initial > transaction generate an error ? What would be a possible fix to avoid > these transaction errors for these 31 (unneded ?) pci_scan_slot() calls > on the initial bus ? I see this too on my P5020 based platform. No fix yet, for now disabling the EDAC. Thanks, Rajat > > Best Regards, > > Valentin ��.n��������+%������w��{.n�����{���"�)�� jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
