Hi Michael, Thanks for your inputs. On Wed, Mar 5, 2014 at 9:42 AM, Michael Chan <mchan@xxxxxxxxxxxx> wrote: > On Wed, 2014-03-05 at 09:33 +0530, Jagan Teki wrote: >> The driver is not seeing the status block mean - tg3.c driver? > > Yes, tg3 driver. All IRQ events (link change, rx, tx) are in status > block. If tg3 does not see the correct bits and indexes in the status > block, it won't know what to do. In this case, it doesn't see the link > change bit in status block (I suspect), so it is not acknowledging and > clearing the link change event. Status block is DMA'ed from the NIC to > memory. OK. As per your point I've a question here like - the status block is not properly updated (DMA'ed), does this depends on the address range we are advertised on PCIe ranges filed to make sure to use EP- http://devicetree.org/Device_Tree_Usage#PCI_Host_Bridge The reason for asking this is we have two kind of PCIe bridge in separate boards where one is working fine by showing below log, and other we could see this issue. # ifconfig eth0 172.16.0.2 up RC: handler tg3_interrupt_tagged: ++status_tag = 0x1 write status = 0x1 --status_tag = 0x1 RC: handler tg3_interrupt_tagged: ++status_tag = 0x1 write status = 0x1 --status_tag = 0x1 tg3_poll: tag = 0x1 calling tg3_int_reenable val = 0x01000000 > >> Does it relates to ISR or addressing of PCIe RC driver, I'm doing >> nothing on my PCIe RC driver just read the legacy INT# status and >> return. > > RC stands for what? Root Complex? I don't know what an RC driver does. Yes, Root Complex driver in PCIe bridge. -- Jagan. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
