On Thursday 27 February 2014 14:13:22 Liviu Dudau wrote:
>
> It is useful for host bridge drivers as this is the only place where we store
> the physical CPU address for the IO range. This is then needed when setting up the
> translation registers. Also used when calling the pci_ioremap_io function that I'm
> introducing in the AArch64 patches.
I don't understand what translation windows you are talking about. Is this
about how the PCI spaces are mapped into the CPU address space? If so, I
would strongly recommend to have this handled by the boot loader before
calling into the kernel. For ARM32, we have a lot of embedded systems
that require the PCI host driver to set up those windows, but actually
it would be much better to just have the firmware tell us what the setup
is and that use that.
> Whole patch is still under legal review, but the fragment for setting up the ATR looks
> like this:
>
> list_for_each_entry(window, &bridge->windows, list) {
> res = window->res;
> offset = window->offset;
> wsize = ilog2(resource_size(res)) - 1;
>
> if (resource_type(res) == IORESOURCE_MEM)
> update_atr_entry(pp->base + ATR_REG_whatever,
> res->start, /* CPU address */
> res->start - offset, /* PCI address */
> 0, wsize);
> else if (resource_type(res) == IORESOURCE_IO) {
> io_offset = pci_ioremap_io(res, bridge->io_base + offset);
> update_atr_entry(pp->base + ATR_REG_whatever,
> bridge->io_base + res->start + offset, /* CPU address */
> res->start, /* PCI address */
> 0x20000, wsize);
> }
> }
Hmm, I again don't see how 'bridge->io_base + res->start + offset' is
the correct address here. What is it you are trying to pass into
update_atr_entry()?
Arnd
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