On Thursday, February 20, 2014 10:34 PM, Mohit KUMAR DCG wrote:
> Thursday, February 20, 2014 5:43 PM, Kishon Vijay Abraham I wrote:
> > On Thursday 20 February 2014 05:28 PM, Mohit KUMAR DCG wrote:
> > > On Thursday, February 20, 2014 5:08 PM, Kishon Vijay Abraham I wrote:
> > >> On Thursday 20 February 2014 10:52 AM, Mohit Kumar wrote:
> > >>> This patch correct iATU programming for cfg1, io and mem viewport.
> > >>> Enable ATU only after configuring it.
> > >>
> > >> Does this patch actually fixes device enumeration behind a PCIe-pci
> > >> bridge or this is more of cleaning up the sequence?
> > >>
> > > - This patch corrects ATU programming sequence. I am not aware of any
> > > such issue with current driver. Pls specify which bridge do you use in your
> > setup and what is the problem?
> >
> > I tried with card [1], it had a PLX bridge chip. It couldn't read the configuration
> > space of the device connected to the PCIe-PCI bridge.
> >
> - I don’t have the mentioned card with me, but we are successfully using Lecroy PTC switch
> and SIL3124-2CB364 PCI-X compatible RAID card.
>
> May be Jingoo or others can also comment if they are using PCI bridge card.
>
Hi Kishon,
Nice to see you again. :-)
I don't have PCIe-PCI bridge. Currently, I can test Ethernet cards
and SATA cards.
By the way, according to the Datasheet, PCIE_ATU_CR1 setting can be
followed by PCIE_ATU_CR2 setting as below:
1. Setup the Index Register.
2. Setup the Region Base and Limit Address Registers.
3. Setup the Target Address Registers.
4. Configure the region through the Region Control 1 Register.
5. Enable the region.
Thus, how about testing the following patch?
I also moved PCIE_ATU_CR1 as well as PCIE_ATU_CR2.
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6d23d8c..4017abf 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -521,14 +521,14 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
/* Program viewport 1 : OUTBOUND : CFG1 */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
PCIE_ATU_LIMIT);
dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
@@ -536,8 +536,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
/* Program viewport 0 : OUTBOUND : MEM */
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
@@ -536,8 +536,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
/* Program viewport 0 : OUTBOUND : MEM */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
@@ -545,6 +543,8 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
@@ -552,8 +552,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
/* Program viewport 1 : OUTBOUND : IO */
dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
PCIE_ATU_VIEWPORT);
- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
@@ -561,6 +559,8 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
PCIE_ATU_UPPER_TARGET);
+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
+ dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
}
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
--
1.7.10.4
Best regards,
Jingoo Han
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