On Feb 19, 2014 21:04 (GMT+09:00), Mohit Kumar write:
> The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1).
> The BARs can be configured as follows:
>
> - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR.
> - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs
>
> This patch corrects 64-bit, non-prefetchable memory BAR configuration
> implemented in dw driver.
>
> Signed-off-by: Mohit Kumar <mohit.kumar@xxxxxx>
> Cc: Pratyush Anand <pratyush.anand@xxxxxx>
> Cc: Jingoo Han <jg1.han@xxxxxxxxxxx>
> Cc: Arnd Bergmann <arnd@xxxxxxxx>
> Cc: spear-devel@xxxxxxxxxxx
> Cc: linux-pci@xxxxxxxxxxxxxxx
I works properly on Exynos platfrom.
Acked-by: Jingoo Han <jg1.han@xxxxxxxxxxx>
Best regards,
Jingoo Han
> ---
> drivers/pci/host/pcie-designware.c | 2 +-
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