On Thu, Feb 20, 2014 at 09:55:18AM +0100, Thomas Petazzoni wrote: > Does that make sense? Keep in mind that I'm still not completely > familiar with the PCI terminology, so maybe the above explanation does > not use the right terms. Stated another way, the Marvel PCI-E to PCI-E bridge config space has a quirk that requires the window BARs to be aligned on their size and sized to a power of 2. The first requirement is already being handled by hooking through ARM's 'align_resource' callback. One avenue would be to have mvebu_pcie_align_resource return a struct resource and manipulate the size as well. Assuming the PCI core will accommodate that. Jason -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
