On Wed, Feb 19, 2014 at 09:48:48PM +0100, Arnd Bergmann wrote: > Hmm, we'll have to think about that. From a DT perspective, we try > to keep things local to the node using it, so listing only the > registers we are allowed to access is more natural. If I understand the restriction properly, in a modern PCI-E world it boils down to a limition on the configuration of each PCI-PCI root port bridge (eg, a limited range of valid bus values, and apertures) AFAIK it comes from the hidden per-socket routing registers that the firwmare configures. Range X->Y (bus #, IO and MMIO) will be routed to a specific physical socket, and then the PCI-E bridges in that socket claim the transatcion based on their local config to select the ultimate egress port. So describing and restricting the bridge DT node itself, under a single top level PCI domain stanza seems pretty reasonable. As does containing the restrictions in a HW driver with knowledge of the hidden registers, especially for firmware-less embedded. This is part of what mvebu is doing already. Jason -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
