On Tue, 2013-12-17 at 15:24 -0700, Bjorn Helgaas wrote:
> On Tue, Dec 17, 2013 at 3:12 PM, Alex Williamson
> <alex.williamson@xxxxxxxxxx> wrote:
> > On Mon, 2013-12-16 at 17:48 -0700, Bjorn Helgaas wrote:
> >> On Tue, Dec 10, 2013 at 11:48:45AM -0700, Alex Williamson wrote:
>
> >> > +static void pci_vc_load_arb_table(struct pci_dev *dev, int pos)
> >> > +{
> >> > + u32 ctrl;
> >> > +
> >> > + pci_read_config_dword(dev, pos + PCI_VC_PORT_CTRL, &ctrl);
> >> > + pci_write_config_dword(dev, pos + PCI_VC_PORT_CTRL, ctrl | 1);
> >> > + if (pci_wait_for_pending(dev, pos + PCI_VC_PORT_STATUS, 1))
>
> >> spec says these are 16-bit registers; shouldn't these be "word" accesses?
> >
> > The control registers are 32-bit, the status registers are 16-bit.
> > pci_wait_for_pending uses word access.
>
> The "VC Resource Control Registers" at offset 14h + (n * 0Ch) are 32
> bits, but I was referring to the PCI_VC_PORT_CTRL accesses, sorry I
> didn't make that clear. I'm looking at 7.11.4 "Port VC Control
> Register" at offset 12 (0Ch), and that one looks like 16 bits to me.
Indeed it is. Will fix. Thanks,
Alex
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