On Thu, Dec 05, 2013 at 05:19:55PM -0700, Bjorn Helgaas wrote: > pci_setup_bridge_io() accessed PCI_IO_BASE and PCI_IO_LIMIT using dword > (32-bit) reads and writes, which also access the Secondary Status register. > Since the Secondary Status register is in the upper 16 bits of the dword, > and we preserved those upper 16 bits, this had the effect of clearing any > of the write-1-to-clear bits that happened to be set in the Secondary > Status register. This is a good catch! > - pci_write_config_dword(bridge, PCI_IO_BASE, l); > + pci_write_config_word(bridge, PCI_IO_BASE, l); But this is a problem :( tegra and mvebu at least do not have HW to do non-32 bit writes, so their implementation of pci_write_config_word does the RMW internally and will still have this same bug. I think you have to keep the 32 bit write here, but zero the write-one-to-clear bits :( Regards, Jason -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
