On Wednesday, November 27, 2013 5:44 PM, Marek Vasut wrote: > Wednesday, November 27, 2013 1:30 PM, Pratyush Anand wrote: > > On Wed, Nov 27, 2013 at 05:10:43AM +0800, Marek Vasut wrote: > > > From: Tim Harvey <tharvey@xxxxxxxxxxxxx> > > > > > > The IMX6 iATU is used for address translation between the AXI bus > > > address space and PCI address space. This is used for type0 and type1 > > > config cycles but is not necessary for outbound io/mem regions. > > > > > > This patch removes the calls that inappropriately re-configures the ATU > > > viewport for outbound memory and IO after config cycles and removes them > > > altogether as they are not necessary. > > > > Yes, they are not necessary for all the cases where translation is one > > to one. So so for sure all the platform till now introduced should > > work. > > But, what about a platform where memory translation is not one to one? > > > > Existing code should work with all sort of memory translation on a > > platform having atleast two viewports capable of programming any type > > of outbound transaction. > > Full ACK, that's why it's called RFC. > > > > This resolves issues with PCI devices behind switches and has been tested > > > with a Gige device behind a PLX PEX860x switch. More testing is needed > > > for other configurations. > > > > I do not understand if MX6 has 4 Outbound Viewport then how this patch > > helps? > > -- PCI devices behind switches would not have been working because > > CFG1 transaction would not have been correct. > > -- It works with this patch. This patch changes viewport for CFG1 from > > 1 to 0. > > -- Can it be possible that MX6 has some restriction on viewport > > programming capability. I mean,like only viewport0 can be programmed > > for CFG0/1? > > Tim ? > > Here is the MX6 datasheet [1], the section 48.3.9.1.1 and 48.3.9.1.2 describe > the iATU configuration on MX6. My understanding from this description is that > the MX6 has 4 inbound and 4 outbound iATU regions. Am I wrong ? The numbers of inbound and outbound are hardware-configurable features. Thus, these numbers can be confirmed by Freescale hardware engineers. How about asking Freescale hardware engineers, if possible? Best regards, Jingoo Han > > [1] http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf > > > Otherwise I do not find any convincing reason that why this patch > > helps in resolving issues with PCI devices behind switches. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
