On Thu, Nov 21, 2013 at 1:05 PM, Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote: > On Thu, Nov 21, 2013 at 12:18 PM, Yinghai Lu <yinghai@xxxxxxxxxx> wrote: >> >> 3. or more generic, treat all pci BAR 32bit prefetechable as normal >> MMIO32 during allocation. aka mmio prefectechable will be used for pci >> bridge that support 64bit mmio pref and leave bridge's 32bit only pref >> bar register blank. >> >> Bjorn, Linus, >> Are you happy with No 3? > > I don't think I understand your #3. If there's a 32-bit device behind > the bridge, it will need to be in the low 4G, so you can't use the > 64-bit window because it will be out of range. So that wouldn't work. > So you'd need to have a bridge window in the low 32-bit area too if > there are any 32-bit devices behind the bridge. bridge should have two mmio, mmio nonpref: it only can be 32bit mmio pref: it could be 32bit only or 64bit. and we are ok to put child pref range under nonpref range from bridge. Here are suggestion is: assume mmio pref: will be use for 64bit pref only, and if the mmio pref does not support 64bit, we just ignore it. If devices under that bridge need pref, we will just use range from bridge's nonpref mmio. > > Also, haven't we tried the "try to allocate 64-bit devices in high > memory" and it has always failed because there are broken devices? In my test setups, it is always working. --- only with Intel network devices and Mellanox Infiniband cards and storage cards from Qlogic and Emulex. Thanks Yinghai -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
