Without forcing the PCIe core into Gen1 operation, the PCIe switch
attached directly to the PCIe port is not recognised at all. The
PCIe switch is Gen2 capable to make this issue even more puzzling.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
Cc: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Cc: Frank Li <lznuaa@xxxxxxxxx>
Cc: Jingoo Han <jg1.han@xxxxxxxxxxx>
Cc: Mohit KUMAR <Mohit.KUMAR@xxxxxx>
Cc: Pratyush Anand <pratyush.anand@xxxxxx>
Cc: Richard Zhu <r65037@xxxxxxxxxxxxx>
Cc: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Cc: Sean Cross <xobs@xxxxxxxxxx>
Cc: Shawn Guo <shawn.guo@xxxxxxxxxx>
Cc: Siva Reddy Kallam <siva.kallam@xxxxxxxxxxx>
Cc: Srikanth T Shivanand <ts.srikanth@xxxxxxxxxxx>
Cc: Tim Harvey <tharvey@xxxxxxxxxxxxx>
Cc: Troy Kisky <troy.kisky@xxxxxxxxxxxxxxxxxxx>
Cc: Yinghai Lu <yinghai@xxxxxxxxxx>
---
drivers/pci/host/pci-imx6.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index ca8c5de..8402e9a 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -321,6 +321,7 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
{
int count = 0;
struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+ uint32_t tmp;
imx6_pcie_assert_core_reset(pp);
@@ -330,13 +331,23 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
dw_pcie_setup_rc(pp);
+ /*
+ * FIXME:
+ * Force Gen1 operation. In case the IP block is in Gen2 operation
+ * mode, it does not detect the PCIe switch at all.
+ */
+ tmp = readl(pp->dbi_base + 0x7c);
+ tmp &= ~0xf;
+ tmp |= 0x1;
+ writel(tmp, pp->dbi_base + 0x7c);
+
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
while (!dw_pcie_link_up(pp)) {
usleep_range(100, 1000);
count++;
- if (count >= 10) {
+ if (count >= 200) {
dev_err(pp->dev, "phy link never came up\n");
dev_dbg(pp->dev,
"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
--
1.8.4.rc3
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