Hi Richard, > Hi Tim: > As I know that the clock of pcie controller should be always running. > There are not clock gate on/off operations in host driver after the > initialization. I think the problem might happen when the PCIe device (Ethernet adapter) is bus- master and either initiates PCIe->AXI->memory write or memory->AXI->PCIe read transfer. This is because when the Intel ethernet (igb) is probed, it only uses the MEM window that's mapped into the AXI space (that window at 0x01100000). On the other hand, when some packet is transfered, the Intel controller operates with structures in DRAM directly. And the stall only happens when the interface either receives or attempts to send a packet. Is this theory of mine even reasonable? If this doesn't work properly, could this stall the CPU? How can I check if this works correctly? What can I try if it does not? Thanks! btw. Please be careful about the top-posting ;-) Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
