Hi Bjorn, > On Thu, Oct 10, 2013 at 11:39 AM, Marek Vasut <marex@xxxxxxx> wrote: > > Hi Bjorn, > > > >> [+cc Yinghai] > >> > >> On Thu, Oct 10, 2013 at 9:58 AM, Marek Vasut <marex@xxxxxxx> wrote: > >> >> On Thu, Oct 10, 2013 at 4:25 AM, Marek Vasut <marex@xxxxxxx> wrote: > >> > I tried you suggestion, this is what I got now (and with V7 of the > >> > patches): > >> > > >> > Note that my topology is: rootport->2_port_switch->ethernet_chip , the > >> > other port of the switch is not used . > >> > > >> > imx6q-pcie 1ffc000.pcie: phy link never came up After discussing with Tim a little, looks like a clock bit was missing. The above line was the cause of all the issues. Now I can probe the bus, but I still need more patches: This dirty patch here limits the PCIe operation to GEN1 only. It's based on this Freescale patch [1]. Without this change, the PCIe switch is not detected. Any idea why? (I also had to increase the PHY startup delay to get GEN1 going). [1] https://www.osadl.org/monitoring/patches/r8s7/1342-ENGR00180230-MX6-PCIE- enlarge-the-eye-diagram-and-fo.patch diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 32b30ca..df2838b 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -330,13 +330,16 @@ static void imx6_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); +// Enable GEN1 +writel(((readl(pp->dbi_base + 0x7c) & 0xfffffff0) | 0x1), pp->dbi_base + 0x7c); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); while (!dw_pcie_link_up(pp)) { usleep_range(100, 1000); count++; - if (count >= 10) { + if (count >= 200) { dev_err(pp->dev, "phy link never came up\n"); dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
