> -----Original Message----- > From: linux-kernel-owner@xxxxxxxxxxxxxxx [mailto:linux-kernel- > owner@xxxxxxxxxxxxxxx] On Behalf Of Bhushan Bharat-R65777 > Sent: Tuesday, October 08, 2013 10:40 PM > To: joro@xxxxxxxxxx; Bjorn Helgaas > Cc: alex.williamson@xxxxxxxxxx; benh@xxxxxxxxxxxxxxxxxxx; > galak@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linuxppc- > dev@xxxxxxxxxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx; agraf@xxxxxxx; Wood > Scott-B07421; iommu@xxxxxxxxxxxxxxxxxxxxxxxxxx > Subject: RE: [PATCH 1/7] powerpc: Add interface to get msi region > information > > > > > -----Original Message----- > > From: joro@xxxxxxxxxx [mailto:joro@xxxxxxxxxx] > > Sent: Tuesday, October 08, 2013 10:32 PM > > To: Bjorn Helgaas > > Cc: Bhushan Bharat-R65777; alex.williamson@xxxxxxxxxx; > > benh@xxxxxxxxxxxxxxxxxxx; galak@xxxxxxxxxxxxxxxxxxx; > > linux-kernel@xxxxxxxxxxxxxxx; linuxppc- dev@xxxxxxxxxxxxxxxx; > > linux-pci@xxxxxxxxxxxxxxx; agraf@xxxxxxx; Wood Scott- B07421; > > iommu@xxxxxxxxxxxxxxxxxxxxxxxxxx > > Subject: Re: [PATCH 1/7] powerpc: Add interface to get msi region > > information > > > > On Tue, Oct 08, 2013 at 10:47:49AM -0600, Bjorn Helgaas wrote: > > > I still have no idea what an "aperture type IOMMU" is, other than > > > that it is "different." > > > > An aperture based IOMMU is basically any GART-like IOMMU which can > > only remap a small window (the aperture) of the DMA address space. DMA > > outside of that window is either blocked completly or passed through > untranslated. > > It is completely blocked for Freescale PAMU. > So for this type of iommu what we have to do is to create a MSI mapping > just after guest physical address, Example: guest have a 512M of memory > then we create window of 1G (because of power of 2 requirement), then we > have to FIT MSI just after 512M of guest. [Sethi Varun-B16395] PAMU (FSL IOMMU) has a concept of primary window and subwindows. Primary window corresponds to the complete guest iova address space (including MSI space), with respect to IOMMU_API this is termed as geometry . IOVA Base of subwindow is determined from the number of subwindows (configurable using iommu API). Subwindows allow for handling physically discontiguous memory. PAMU translates device iova accesses to actual physical address. MSI mapping would be addressed by a subwindow, with iova base starting at the end of the guest iova space. VFIO code creates a PAMU window (also defines number of subwindow) to map the guest iova space + msi space. The interface defined by this patch queries the PAMU driver to get the iova mapping for the msi region assigned to the PCIe device (assigned to the guest). -Varun -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
