On Tue, Sep 24, 2013 at 5:19 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote: > On Tue, Sep 10, 2013 at 04:10:43PM -0700, Todd E Brandt wrote: >> The latest Ivy Bridge Intel chipsets have a hardware optimization which > > You said "Ivy Bridge" above but use "Haswell" below. Let me know if > anything needs to be corrected here. Reading this again, the text really doesn't make sense as-is. So please confirm what this should say. It sure looks like it should say "The latest *Haswell* Intel chipsets ..." If you really mean "Ivy Bridge," then you should say something about how Haswell is related to Ivy Bridge. No doubt this is all obvious to Intel folks, but it's not to me :) Bjorn >> allows on-chip PCI devices to ignore the 10ms delay before entering >> or exitting D3 suspend. >> >> This patch implements the optimization as a pci quirk, since we want >> tight control over which devices use it. This way we can test each device >> individually to be sure there are no issues before we enable the quirk. >> The first set of devices are from the Haswell platform, which includes >> every PCI device that is on the northbridge and southbridge. >> >> After testing this patch reduces the haswell suspend time from 93 ms to >> 47 ms and resume time from 160 ms to 64 ms. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
