Hello, On Wed, Sep 04, 2013 at 06:14:43PM +0200, Alexander Gordeev wrote: > 1. We do not support sharing MSI messages since there is no appropriate > interrupt handling for it. I am not sure if any hardware supports it at > all. This assumption is just for clarity here. I don't think it even matters. If we can configure all MSIs, good. If not, using single interrupt is good enough. Being able to allocate only some of the interrupts is highly unlikely to begin with and there's no reason to meddle with extra complexity. > 2. We can not just read out MMC value and try to write it to MME, because > we are not sure the hardware honours the specification. I.e. in case of 6 > ports and MMC value of 16 the value of 8 in MME could enable multiple MSIs > while the value of 16 could enforce MRSM. Contradicts to the AHCI > specification, but look how weird ICH is [4]. > > 3. Enabling more MSIs than needed (MME == MMC instead of MME < MMC) could > lead to unnecessary allocation of internal device resources. Bit lame, but > still true. > > 4. We can not derive the value of MME needed from the number of ports, at > least in case of ICH. I.e. with 6 ports and MMC value of 16 the value of 8 > in MME is what would be expected according to the AHCI specification. But > the ICH reserves it and MRSMs in case 8 is written to MME. > > So to cover all the above assumptions we need to scan from lowest possible > and watch the MRSM bit is unset. I don't think it's necessary / a good idea to try to support everything. Just following the spec would be fine. If that doesn't work for too many devices, maybe just do one fallback? Thanks. -- tejun -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
