VIA chipset with Root Port under a bridge

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Shaohua, your commit 8e822df700 references a VIA chipset with a Root
Port under a bridge, and that commit adds a special case to disable
ASPM for that situation.

I know this is pretty old (the commit is from 2009), but do you have
any more details about that system?  A pointer to the original problem
report, lspci output, dmesg output, etc.?

I'm concerned because other parts of PCI make assumptions about Root
Port topology, e.g., in MPS configuration, and we might need to make
similar changes elsewhere.

Bjorn
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