On 08/05/2013 12:37 PM, Alex Williamson wrote: > The PCI spec indicates that with stable power, reset needs to be > asserted for a minimum of 1ms (Trst). Seems like we should be able > to assume power is stable for a runtime secondary bus reset. The > current code has always used 100ms with no explanation where that > came from. The aer_do_secondary_bus_reset() function uses 2ms, but > that seems to be a misinterpretation of the PCIe spec, where hot > reset is implemented by TS1 ordered sets containing the hot reset > command. After a 2ms delay the state machine enters the detect state, > but to generate a link down, only two consecutive TS1 hot reset > ordered sets are requred. 1ms should be plenty for that. The reason for doing a 2ms sleep is because the are supposed to be sending the Hot Reset TS1 Ordered-Sets continuously for 2ms per all of the documents I have read. The 1ms number you quote is the minimum time for a conventional PCI bus. I'm not completely sure of that applies as well to PCIe, nor does it represent the maximum recommended value. If we stop early we risk not resetting the full device tree on the secondary bus which is the bug I was resolving by adding the 2ms delay. Previously we saw that some devices were only getting their PCIe link retrained without performing a hot reset when the bit was not held for long enough. I would prefer to keep this at 2 ms in order to account for the fact that PCIe has to go though link recovery states before it can perform the hot reset. Thanks, Alex -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
