Re: [PATCH 4/4] PCI: fix the io resource alignment calculation in pbus_size_io()

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On Tue, Aug 06, 2013 at 07:44:21AM -0600, Bjorn Helgaas wrote:
>On Tue, Aug 06, 2013 at 02:19:24PM +0800, Wei Yang wrote:
>> On Mon, Aug 05, 2013 at 11:58:50AM -0600, Bjorn Helgaas wrote:
>> >[+cc Yinghai]
>> >
>> >On Fri, Aug 2, 2013 at 3:31 AM, Wei Yang <weiyang@xxxxxxxxxxxxxxxxxx> wrote:
>> >> In commit 462d9303 ("PCI: Align P2P windows using pcibios_window_alignment()"),
>> >> it introduce a new method to calculate the window alignment of P2P bridge.
>> >>
>> >> When the io_window_1k is set,  the calculation for the io resource alignment
>> >> is different from the original one. In the original logic before 462d9303,
>> >> the alignment is no bigger than 4K even the io_window_1k is set. The logic
>> >> introduced in 462d9303 will limit the alignment to 1k in this case.
>> >>
>> >> This patch fix this issue.
>> >
>> >Presumably this fixes a bug, but you don't say what it is.  "different
>> >from the original" is not a description of a problem.  You need
>> >something like "with the current code, we allocate the wrong window
>> >size in situation X, or we allocate a window with incorrect alignment
>> >in situation Y, etc."
>> >
>> 
>> With current code, we allocate the wrong window size when upstream bridge
>> could be 1k aligned and one of the downstream port is 4k aligned.
>> 
>> In this case, the "min_align" should be 4k. But the current code set
>> "min_align" to 1k.
>

Hmm... sorry I should say. 

With current code, we allocate the wrong window size and alignment when upstream 
bridge could be 1k aligned and one of the downstream port is 4k aligned.

In this case, the "min_align" should be 4k. But the current code set
"min_align" to 1k.

>I would expect that we allocate a window with incorrect *alignment*,
>not incorrect size.  If you include a dmesg log and lspci output and point
>out the problem, that will avoid a lot of confusion.

Agree. 

I notice this potential problem during the code reading and found
the io_window_1k is set only for Intel P64H2 bridge. Currently I don't have
this device, not sure how to create this senario.

Sorry for the confusion, I should state the problem more clearly.

>
>Bjorn

-- 
Richard Yang
Help you, Help me

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