On Wednesday, July 10, 2013 11:02 PM, Kishon Vijay Abraham I: > On Friday 05 July 2013 01:59 PM, Jingoo Han wrote: > > Exynos PCIe IP consists of Synopsys specific part and Exynos > > specific part. Only core block is a Synopsys designware part; > > other parts are Exynos specific. > > Also, the Synopsys designware part can be shared with other > > platforms; thus, it can be split two parts such as Synopsys > > designware part and Exynos specific part. > > Thanks for doing that :-) > > I'll be using the synopsys specific part as Jacinto6 also uses the same pcie > core. Once I start implementing, I'll have some queries and comments ;-) Hi Kishon, OK, I see. I will send v2 patch. Also, I will be CC'ing you. :) Best regards, Jingoo Han -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
