On Friday, July 05, 2013 7:44 PM, Pratyush Anand wrote:
> On 7/5/2013 1:59 PM, Jingoo Han wrote:
> > Exynos PCIe IP consists of Synopsys specific part and Exynos
> > specific part. Only core block is a Synopsys designware part;
> > other parts are Exynos specific.
> > Also, the Synopsys designware part can be shared with other
> > platforms; thus, it can be split two parts such as Synopsys
> > designware part and Exynos specific part.
> >
>
> A quick and nice job :)
> Just few minor comments.
>
> > Signed-off-by: Jingoo Han <jg1.han@xxxxxxxxxxx>
> > Cc: Pratyush Anand <pratyush.anand@xxxxxx>
> > Cc: Mohit KUMAR <Mohit.KUMAR@xxxxxx>
> > ---
> > drivers/pci/host/Makefile | 1 +
> > drivers/pci/host/pcie-designware.c | 907 +++++++-----------------------------
> > drivers/pci/host/pcie-designware.h | 72 +++
> > drivers/pci/host/pcie-exynos.c | 619 ++++++++++++++++++++++++
> > 4 files changed, 862 insertions(+), 737 deletions(-)
> > create mode 100644 drivers/pci/host/pcie-designware.h
> > create mode 100644 drivers/pci/host/pcie-exynos.c
> >
[...]
> > -static inline void readl_rc(struct pcie_port *pp, void *dbi_base, u32 *val)
> > +static inline void dw_pcie_readl_rc(struct pcie_port *pp, void *dbi_base,
> > + u32 *val)
>
> dbi_base is part of pp. So why to pass 3 args?
Sorry, this variable does not mean dbi_base;
it means 'dbi_base + offset'.
dw_pcie_{readl/writel}_rc() are called as below:
dw_pcie_readl_rc(pp, dbi_base + PCIE_PORT_LINK_CONTROL, &val);
dw_pcie_writel_rc(pp, val, dbi_base + PCIE_PORT_LINK_CONTROL);
Thus, 'dbi_base' can be replaced with 'dbi_addr'.
Best regards,
Jingoo Han
>
> > {
> > - exynos_pcie_sideband_dbi_r_mode(pp, true);
> > - *val = readl(dbi_base);
> > - exynos_pcie_sideband_dbi_r_mode(pp, false);
> > - return;
> > + if (pp->ops->readl_rc)
> > + pp->ops->readl_rc(pp, dbi_base, val);
>
> ditto
>
> > + else
> > + *val = readl(dbi_base);
> > }
> >
> > -static inline void writel_rc(struct pcie_port *pp, u32 val, void *dbi_base)
> > +static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val,
> > + void *dbi_base)
>
> ditto
>
> > {
> > - exynos_pcie_sideband_dbi_w_mode(pp, true);
> > - writel(val, dbi_base);
> > - exynos_pcie_sideband_dbi_w_mode(pp, false);
> > - return;
> > + if (pp->ops->writel_rc)
> > + pp->ops->writel_rc(pp, val, dbi_base);
>
> ditto
>
> > + else
> > + writel(val, dbi_base);
> > }
>
>
> Regards
> Pratyush
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