Hello,
I am inspecting the MSI-X setup of some PCIe devices and have questions
about the output of lspci.
It looks something like this:
Capabilities: [50] MSI-X: Enable+ Count=32 Masked-
Vector table: BAR=0 offset=00002000
PBA: BAR=0 offset=00003000
As far as I understand the PCI 3.0 specification MSI-X capabilities
define a 32 bit register for the upper address portion of the MSI target
addresses (at capability offset 4) and another 32 bit register pointing
to the BAR and inter-BAR offset for the table of lower address portions
of the MSI target addresses (at capability offset 8).
Why are there two lines in the lspci output indicating some BAR and
offset? What do they mean?
Looking at the source code of pciutils (ls-caps.c) indicates that the
PBA line is the information pointing to the table of MSI-X entries,
while the vector table line is actually the upper 32bit of each MSI
target address. This should however not be split into BAR and offset in
that case, I believe.
What did I miss?
Thanks for clarifying,
David
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