On Monday, April 22, 2013 05:10:26 PM Bjorn Helgaas wrote:
> The Power Management Capability (PCI_CAP_ID_PM == 0x01) is defined by PCI
> and must appear in the 256-byte PCI Configuration Space from 0-0xff. It
> cannot be in the PCIe Extended Configuration space from 0x100-0xfff, so
> we only need a u8 to hold its offset.
>
> Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
> CC: "Rafael J. Wysocki" <rjw@xxxxxxx>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@xxxxxxxxx>
> ---
> include/linux/pci.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 2461033a..9587d4d 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -249,8 +249,7 @@ struct pci_dev {
> pci_power_t current_state; /* Current operating state. In ACPI-speak,
> this is D0-D3, D0 being fully functional,
> and D3 being off. */
> - int pm_cap; /* PM capability offset in the
> - configuration space */
> + u8 pm_cap; /* PM capability offset */
> unsigned int pme_support:5; /* Bitmask of states from which PME#
> can be generated */
> unsigned int pme_interrupt:1;
>
--
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.
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